A/D converters are incorporated many recently introduced microcontroller products. Almost all have resolution ranging from 8 to 10 bits, but A/D converters with 10-bit resolution don't always have to be used to their full potential. For practical purposes, a resolution of 8 bits or even less is often sufficient.
[Example of required specifications]
Few key inputs are used for relatively simple A/D converter applications. When selecting "Key switch input in microcontrollers (part 2)"as the specific hardware configuration, each pressed switch is detected by the A/D converter. The correspondence between pressed switches and the A/D converter's input voltage is shown below.
|Input voltage||Pressed switch|
|0.8VDD or above||None|
|0.6 - 0.8VDD||SW4|
|0.4 - 0.6VDD||SW3|
|0.2 - 0.4VDD||SW2|
|0.2VDD or less||SW1|
The changes in input voltage when the switches are pressed and released are gentle changes. If the applied capacitor is rated at approximately 1000 pF, a few hundred µs are needed for the voltage to become stabilized.
During this period, the input voltage traverses areas that correspond to different key inputs and changes. Therefore, to prevent detection errors during this period, the detection criteria must include more than just the input voltage. Consideration must also be given to the processing used to detect when the input voltage has become stable. Consequently, in addition to implementing noise reduction measures, 16 conversions are averaged to yield valid conversion results by which these changes can be monitored.
Coffee Break |
Chattering occurs in the switches used for this. To avoid chattering effects, waveforms must be smoothed. In this case, this function is performed by a resistor for voltage setting and a time constant circuit including a capacitor for analog input. Therefore, the circuit's time constant cannot be set too small.
A similar noise reducing effect can be produced by taking the average from multiple A/D conversions. However, if chattering effects are not minimized at a stage prior to A/D conversion, the conversion results may contain large discrepancies.
In addition, when performing A/D conversions for other channels, it may affect other operations. Consequently, it is important to avoid chattering effects in time constant circuits.
Key inputs are judged based on the valid conversion results obtained via this approach.
[Setting judgment criteria]
Specific judgment criteria are set as follows. The graph below illustrates an example of voltage change that occurs when no keys are pressed (0.9VDD). When judgments are made at an interval of approximately 500 µs, any change of 0.1VDD or less can be detected as entering the target voltage range. Therefore, judgments are made at changes of VDD/16 or less as a precaution.
In this case, the 78K0S/KY1+ is operated using an 8 MHz high-speed internal oscillator, using the ANI0 pin, and the A/D conversion time is 28 µs. Only the higher 8 bits are used for results.
The watchdog timer will not be used, and is therefore stopped.
[Program configuration (general)]
The program blocks include an initialization block, an interrupt servicing block for A/D conversion completion interrupts, a main processing block and a key input judgment block.
- Initialization block
This block initializes variables, stops the watchdog timer, waits for the power supply voltage to reach at least 4V to enable 8 MHz operation with the high-speed internal oscillator, and performs initialization for A/D conversion and interrupts.
- Interrupt servicing block
Interrupt servicing influences the overall processing time, so it must be performed as quickly as possible. Consequently, simple processing is performed whenever possible. Specifically, the higher 8 bits of the A/D conversion results are accumulated and the obtained result (carried from 8 bits) is used to detect changes. (If the result matches the previous time's value, 0 is set to the enabled flag and the result is reported.)
- Main processing
During main processing, the result obtained from interrupt servicing is checked and if valid key input has occurred, the key input judgment block is called.
- Key input judgment block
Valid key input is decoded from the obtained input voltages and a branch table is used to determine the corresponding processing block.
The following types of variables are used. COUNTER is a variable used to perform a cumulative count 16 times. It starts from the initial value of 16 and counts down to zero, which indicates that accumulation has been completed.
DATALOG is a variable used to accumulate conversion results. It inserts values in the bits 11 to 0, when 8-bit of conversion result accumulates 16 times. Only the lower 4 bits (bits 11 to 8) of the higher bytes of these results are used for judgments.
OLDDATA stores the higher bytes of the previously accumulated result. This value is compared with the currently accumulated result to determine whether a change has stabilized.
DATAVALID is a flag that indicates when the conversion results are stable. When DATAVALID = 0, it indicates that the conversion result is stable (valid).
• Variable block definition
STACKTOP DSEG IHRAM DS 20H ; Obtain 32 bytes as stack area STACKP: DATWORK DSEG SADDR COUNTER: DS 1 ; Counter for processing judgments DATALOG: DS 2 ; For data accumulation OLDDATA: DS 1 ; For previous data ; Conversion results are set ; to lower four bits when valid DATAVALID: DS 1 ; Valid data flag (0 = valid)
This block includes subroutines that initialize variables and hardware. Such initialization is performed when these subroutines are called from main processing.
For hardware initialization, the watchdog timer and low-speed internal oscillator are both stopped, and a low-voltage detector circuit is used to wait until the power supply voltage reaches at least 4V. Once the power supply has become stable, the CPU clock is set to 8 MHz fR.
The A/D converter is initialized so that the ANI0 channel operates at the lowest speed (one conversion per 28 µs: 8 MHz).
For interrupts, the request flag is cleared and masking of the A/D conversion completion interrupt is canceled. Starting A/D conversion and the CPU's interrupt enable setting is performed by main processing.
• Main initialization
After the stack pointer is set, the initialization subroutine is called and initialization is performed.
CSEG START: MOVW AX,#STACKP MOVW SP,AX CALL !INITRAM ; Initialization of RAM CALL !POWERON ; Wait for power supply activation CALL !INITAD ; A/D initialization CALL !INITINT ; Interrupt initialization
• Initialization subroutine program examples
; ; Initialization of variables ; INITRAM: MOV COUNTER,#16 MOV DATALOG,#0 MOV DATALOG+1,#0 MOV OLDDATA,#NOKEYV MOV DATAVALID,#0FFH RET ; ; Wait for power supply activation ;(wait for power supply voltage to reach at least 4 V) ; POWERON: DI MOV LVIS,#00 ; VLI > 4.1V MOV LVIM,#10000000b ; Start low-voltage detection MOV PCC,#00 ; CPU clock is fx/4 MOV WDTM,#01110111b ; Stop WDT SET1 LSRSTOP ; Stop low-speed internal oscillator MOV A,#50 PONLOOP: DEC A BNZ $PONLOOP ; Wait at least 0.2 ms PONLOOP2: NOP BT LVIF,$PONLOOP2 ; Wait for power supply voltage ; to reach at least 4V MOV PPCC,#00 ; CPU clock is fx=fR RET ; ; Interrupt initialization ; INITINT: MOV IF0,#00 ; Clear interrupt CLR1 ADMK ; Cancel masking of A/D interrupt RET ; ; A/D initialization ; INITAD: MOV ADM,#00111001b ; Set conversion time MOV PMC2,#00000001b ; Use ANI0 SET1 PM2.0 ; Set PM20 to input MOV ADS,#0 ; Select ANI0 RET
(3)Interrupt servicing block
In this case, since this block is only used for A/D conversion completion interrupts, a dummy address (DUMMY) is set for returning without performing any processing to the vector table for other interrupts.
RSTVECTCSEG AT 0 DW START ;00:Vector to reset start processing DW DUMMY ;02: DW DUMMY ;04: DW DUMMY ;06:INTLVI DW DUMMY ;08:INTP0 DW DUMMY ;0A:INTP1 DW DUMMY ;0C:INTTMH1 DW DUMMY ;0E:INTTM000 DW DUMMY ;10:INTTM010 DW ADINT ;12:INTAD
Since the A/D conversion completion interrupt servicing block is executed once every 28µs, processing time should be made as short as possible.
• Processing flow
The processing flow is outlined below.
• A/D conversion completion processing program example
A program example is shown below. This processing is normally completed in 52 clock cycles. When 16 accumulations are completed, 30 clock cycles are added and the total processing is completed in 82 clock cycles.
; ; A/D interrupt servicing ; ADINT: PUSH AX ; 4: MOV A,ADCRH ; 4:Read higher 8 bits of results ADD A,DATALOG ; 4:Accumulate results MOV DATALOG,A ; 4: MOV A,#0 ; 6: ADDC A,DATALOG+1 ; 4: MOV DATALOG+1,A ; 4:Save accumulated results DEC COUNTER ; 4:Count number of times, BNZ $EXITADINT ; 6:exit when 16 times are completed XCH A,OLDDATA ; 4:Refresh results SUB A,OLDDATA ; 4:Detect change MOV DATAVALID,A ; 4:Set detection result to flag MOV DATALOG,#0 ; 6:Clear accumulated results MOV DATALOG+1,#0 ; 6: MOV COUNTER,#16 ; 6:Initialize counter EXITADINT: POP AX ; 4: RETI ; 8: DUMMY: RETI ; Undefined interrupts are ignored
(4)Key input judgment processing
The switches that have been pressed are determined based on the results of A/D conversion completion interrupt servicing and the flag value, after which processing branches to the corresponding processing block. For this amount of input, successive comparison would make the program shorter, but in this case a table is referenced to perform this processing. An initial check as to whether no key input has occurred can be performed to avoid unnecessary analysis.
The table includes the addresses (SW1 to SW4 and NOKEY) of the processing routines corresponding to each key input, and the results obtained from A/D conversion completion interrupt servicing are doubled to calculate the offset. Meanwhile, setting the HL register as a pointer, the processing address is read into the AX register from the table. Branching to the corresponding processing block occurs by branching to the address shown in the AX register.
To return from the processing blocks to main processing, the BR instruction is used.
• Processing flow
The processing flow is outlined below.
• Sample program
; ; Start key input check ; SET1 ADCS ; Start A/D conversion EI MAINLOOP: MOV A,OLDDATA ; Read result CMP A,#NOKEYV ; Key input occurred? BNC $NOKEY ; Exit if no keys input. MOV A,DATAVALID ; Read valid flag and check AND A,A ; if invalid, BNZ $NOKEY ; exit and go to other processing. ; Key input check ; (Branch to processing routine according to data (0 to 15) stored in OLDDATA) ; KEYCHECK: MOV A,OLDDATA ; Read valid data ADD A,A ; Double for address conversion ADD A,#LOW KEYTABLE ; Calculate reference table address MOV L,A MOV A,#HIGH KEYTABLE ADDC A,#0 MOV H,A ; Set HL register as a pointer MOV A,[HL] ; Obtain lower address MOV X,A MOV A,[HL+1] ; Obtain higher address BR AX ; Branch to processing block ; ; Address table for key input decoding ; KEYTABLE: DW SW1 ; 0: DW SW1 ; 1: DW SW1 ; 2: DW SW1 ; 3:0.19VDD DW SW2 ; 4:0.25VDD DW SW2 ; 5: DW SW2 ; 6:0.38VDD DW SW3 ; 7:0.44VDD DW SW3 ; 8: DW SW3 ; 9:0.56VDD DW SW4 ;10:0.63VDD DW SW4 ;11: DW SW4 ;12:0.75VDD DW NOKEY ;13:0.82VDD (not used) DW NOKEY ;14:Not used DW NOKEY ;15:Not used
The option bytes for stopping the low-speed internal oscillator are as follows.
@@OPTB CSEG AT 0080H DB 10011100b DB 11111111b END