Please perform the following settings with fast interrupts disabled by the fast interrupt enable bit (FIEN) in the fast interrupt register (FIR).
(1) Set the vector address that you wish to set to fast interrupt to the CPU's fast interrupt vector register (FINTV).
(2) Set the vector number of a source for use as the fast interrupt to the fast interrupt vector bits (FVCT[7:0]) in the FIR register.
(3) Enable fast interrupts using the FIEN bit in the FIR register.
Setting the source vector to the FVCT [7:0] bits in the FIR register and enabling interrupts by setting the FIEN bit to 1 in (2) and (3) above can be set together by word writing.
The above is the procedure for setting a source for use as the fast interrupt and a vector address. When using fast interrupts, the corresponding interrupt needs to be set separately before enabling fast interrupts.
In addition, fast interrupts are given highest priority, regardless of the settings of the IPRm.IPR[2:0] bits.
Please use the RTFI instruction to return from a fast interrupt.
For details, please refer to Fast Interrupt Register (FIR) in the Interrupt Control Unit chapter of the hardware manual. Please also refer to the information about fast interrupts in the Exceptions and ICU chapters of the hardware manual.