I'd like to confirm the register setting method for the compare match timer (CMT).
To generate an interrupt at a regular interval using the compare match timer, is the value that should be set to the compare match timer constant register (CMCOR) "the set interval (interrupt interval) divided by the resolution (selected clock), minus 1"?
That is correct.
A compare match signal is generated at the last matched state (at the timing at which the CMCNT counter updates the matched count value).
See Timing of Compare Match Interrupt Generation in the user's manual: hardware.
If the value set in the compare match timer constant register (CMCOR) is N, the count value counts from 0 to N. Therefore, the actual count value is N + 1.
If you wish to count to N, set the compare match timer constant register (CMCOR) to N - 1.