Please confirm the following.
1. Please confirm the clock ratio of internal clock (IΦ) and bus clock (BΦ) should NOT be IΦ:BΦ=1:1
In SH7709S/SH7729R/SH7706/SH7727, it is NOT possible to access SDRAM when it is IΦ:BΦ=1:1
(In SH7705/SH7720, it is possible to access SDRAM when it is IΦ:BΦ=1:1)
2. The setting of SDMR (synchronous DRAM mode register) is correct?
1) SH7709S, SH7729R, SH7706, SH7727: Write to SDMR with byte access.
SH7705, SH7720: Write to SDMR with word access.
2) Especially as for the CAS latency, please confirm whether a set value of the wait control register is corresponding to a set value of SDMR. The wait control register here is WCR2 in SH7709S/SH7729R/SH7706/SH7727, and is CS2WCR or CS3WCR in SH7705/SH7720.
3. Please confirm whether MCR (individual memory control register) is correctly set.
4. Please confirm whether the interval of the SDRAM refreshing cycle set by RTCSR (refreshing timer/control register) and RTCOR (refreshing time constant register) fulfills the specified value of SDRAM.
5. Please confirm whether the setup time and the holding time of each signal of SDRAM are fulfilled.