Basically, signals are connected from an output (point) to an input (point). Therefore, in parts configured of many storage elements, such as memory devices, when selecting an individual storage element by means of a point-to-point connection, the number of connected wires must equal the number of storage elements.
It is therefore necessary to reduce the number of wires by encoding the selection signals. When the selection signals are encoded, they become address information. Unlike the selection signals, one item of address information must be output to multiple inputs rather than to just a single input. This creates a bus configuration, known as an address bus.
By using an address bus in this way, the required specifications can be made using only a few signal lines. However, in this case, selection signals are still required for each storage device. As a result, processing to decode the address information must be added. For more information about decoding, see the Decoder FAQ.
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Address information is decoded in order to select one of the storage elements (memory cells) in a memory device, but this information is not simply decoded. Addresses are divided into rows and columns and in a memory device that is configured as a matrix array, the required memory cell is selected by combining two selection lines. This serves to reduce the number of signal lines, improving the level of integration.
Moreover, the wiring can be further reduced by also using the selection lines as data readout lines.
Data also can be handled using a bus configuration. Moreover, by executing bidirectional transfer, the required number of signals can be further reduced. Decoding is not usually required with a data bus, but it must be made clear exactly when the data is valid. This means that in addition to the address and data buses, a separate signal is required for control. An example of writing data using a bus is shown below. In this example, the data on the bus is valid when the WR signal is active (low level).
There are also cases where addresses and data use a common bus to reduce the number of bus signal lines. In this case, use of the bus is determined according to time: during a certain period the bus is used as an address bus, and after that it is used as a data bus. With this method, the addresses and data are multiplexed, hence the term "multiplexed bus". When using a multiplexed bus, a dedicated control signal is required to ensure that the correct address information is fetched by the side receiving the signal. Address control signals with names such as ASTB are used to fetch address information (generate addresses) from the multiplexed bus. Generating addresses from a multiplexed bus requires a latch. For more information about latches, see the Latch FAQ.
Note that with a multiplexed bus, it is important to design the timing so that signals do not conflict while the bus is switching from an address bus to a data bus and vice versa. This is especially true with read operations because the data transfer direction also changes. (This is why an idle cycle-a cycle during which the bus is not accessed-is inserted after a read operation in many microcontrollers.)
This kind of bus can be used to reduce the number of signal lines and wiring, and is an important technology used by the developers of today's microcontrollers. One drawback, however, is the problem of signals becoming bottlenecked as the bus speed increases.