The internal state of logic circuits including microcontrollers is undefined upon power application. Therefore, it is necessary to execute reset to initialize such circuits immediately after power application (Refer to Clock and Reset in the FAQ).
Normally, a dedicated pin (RESET pin) is used to execute reset.
As another way, the circuits contain a function that compares/detects power supply voltages inside the circuits and causes reset execution until the detected voltage become higher than the prescribed value. This function is called Power-On-Clear (POC). The number of external circuits can be reduced by the use of this POC function, contributing to system cost reduction and space saving.
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Many people, when they hear "power supply voltage comparison/detection", believe that the system has an internal booster circuit, and that this circuit generates the reference voltage compared with power supply voltage for the POC. Actually, this is not necessary. A reference voltage that is fixed to a fraction of the prescribed voltage is generated from the power supply voltage. This voltage is compared to a voltage obtained by proportionally reducing the power supply voltage to a fraction with resistors. Function-wise, this is equivalent to comparing the power supply voltage with the prescribed voltage.
The reference voltage of a POC is normally fixed to a constant voltage, but the POC in some ICs that allow the reference voltage to be changed depending on the used voltage through a mask option, etc.
A POC detects the power supply voltage of an individual IC and initializes it. In the case of a system that incorporates multiple ICs each with a built-in POC, since a given IC may be initialized while another is not due to detected voltage variations, the system may malfunction. In such a case, system-wide matching must be implemented through the use of reset signals, etc.
Since EEPROMs that use an I2C bus do not have a reset pin, the above-mentioned problem may occur. In this case, the I2C bus may not operate depending on the state at the time (SDA = low level during data read). When this occurs, the only thing that can be done is to output a dummy clock to the SCL using a port function and wait until the SDA becomes high level.