How do I resolve this situation?
A clock discrepancy may occur between the master and slave due to noise, etc. on the SCL line of the I2C bus. This occurs due to differences in VIH/VIL characteristics or noise elimination capabilities of the two devices causing a difference in whether or not noise, etc. on the SCL line is recognized is a clock.
Please carry out steps 1-3 below for the R8C device on the master side.
1. Set the IICRST bit of the ICCR2 register to 1 (release SCL/SDA output latch of this station).
2. Set the IICRST bit of ICCR2 register to 0 (release internal reset).
3. Check the input level of SCL/SDA (check port input of shared pin).
Depending on the result of 3 above, perform a or b.
a) If SDA and SCL are high level
SDA/SCL of the R8C device on the master side may be fixed to low level. Please carry out step 4 onwards of the procedure shown in FAQNo:107183 .
b) If SDA is low level
SDA of the slave side may be fixed to low level. Please refer to FAQNo:107457 for how to resolve SDA on the slave side being fixed to low level.