The I2C bus uses two signals, a serial clock signal and a serial data signal, to transfer data among multiple devices.
The following three transfer rates are provided:
- Standard mode: up to 100 Kbps
- Fast mode: up to 400 Kbps
- High-speed mode: up to 3.4 Mbps
A device that supports one of the faster transfer rates must also be able to operate when connected to a bus with a slower transfer rate.
A bridge must be used to separate a high-speed mode bus from a standard mode or fast mode bus.
Although communications are synchronized with a serial clock signal, it is still possible to use just one bus to connect several devices (called "masters") that control communications via with a specified communications partner (this is called a "multi-master" system).
Consequently, the protocol not only determines how data is handled but also specifies destination addresses and bus arbitration data.
(1) Connected devices
Devices that can be connected to an I2C bus are classified as follows.
- Master only/TD>: Microcontrollers are mainly used as masters.
- Slave only: EEPROMs, A/D converters, D/A converters, etc.
- Master/slave (shared): For when both master and slave functions are used in a multi-master system
Master-only functions are often used with microcontrollers, such as when connecting to an EEPROM.
Slave functions are also used for some applications.
(2) Interface signal
An interface signal is normally driven via open drain output in order to connect output from multiple devices.
The low-level interface signal is output from a device and the high-level interface signal is provided via a pull-up resistor.
When using high-speed mode, a current source pull-up is included in each device to accelerate the signal's rise time.
Unless otherwise specified, the following descriptions pertain only to the standard bus and fast bus.
Two voltage levels are specified for the bus signals. Since recent microcontroller models enable the power supply to be modified, the pull-up resistor for the I2C bus is connected to VDD, so that the high-level input voltage becomes 0.7VDD (min).
Older devices or other devices with fixed power supply voltages are connected to a 5 V ±5% voltage, which means that the high-level input voltage becomes 3 V (min).
(b) Serial clock (SCL)
Communications are synchronized with this SCL clock signal.
Normally, during communications SCL is output by a master device, and the transmitting device modifies the serial data when SCL is low and retains the data when SCL is high.
However, if the slave device has not been set up for communications, standby is set by setting SCL to the low level, until the data can be synchronized.
If the SDA signal changes when SCL is high, it becomes a control signal for start conditions, stop conditions, etc.
(3)Basic communication methods
To start communications, the master must first obtain bus access.
To do this, it issues a start condition.
This condition is implemented when SDA is set to low level while SCL is at high level.
If either SDA or SCL is already at low level at that time, it means that another master is currently using the bus, so communications must be set to reserved status since no new communications can be started.
If the master device that is not able to use the bus is also able to function as a slave device, communications standby mode is set for it as a slave device.
However, if two or more masters have issued a start condition, it is not possible at this stage to set a priority among them.
In addition to being used to obtain bus access in order to start communications, the start condition is used to switch the data transmit/receive direction between the master and slave devices while the bus is still being accessed.
In such cases, the start condition is called a restart condition.
For a specific example, see [Restart condition] describing restart conditions below.
[Address and arbitration]
After the start condition is issued, 8-bit data that includes a 7-bit address specification and a one-bit transfer direction specification is issued to identify the slave device.
When two or more master devices issue the start condition, it means that each device transmits a slave address.
Since the I2C bus gives higher priority to lower values, communications that are directed to the lowest slave address take priority (i.e., the slave for which SDA is held at low level).
This principle is used to arbitrate bus access.
An ACK (low) signal is returned from the selected slave device at the ninth clock cycle of SCL in response to the transmitted address and transfer direction information. (A wait occurs when SCL is being pulled low at this time.
This wait will be described in [Wait] below.)
If the specified slave device does not exist, there is nothing to pull the bus signal to low level, so an ACK may not be returned.
If an ACK is not returned, the communications are stopped at that point; the master issues a stop condition to stop use of the bus.
Data transfer begins once communications with the slave device has been established.
At that time, during the wait status that is in effect while SCL is at low level, the slave device sets up the transfer direction according to the eighth bit of the address data (transfer direction specification bit). And when this setup is completed, SCL is no longer held low.
Now SCL can be controlled by the master device, and data transfer occurs in synchronization with SCL signals from the master device.
The timing of these operations is illustrated below.
Data is transferred in 8-bit units, and an acknowledge (ACK) signal is returned when the transferred data has been received.
Whenever data is transmitted from a master device to a slave device, an ACK must be returned by the slave device when it receives the data. When an ACK is not received, it informs the master device that the data was not received.
When the master device is the receiving device, if it does not return an ACK in response to the last received data, this informs the slave device that the communication session has ended.
When the slave does not receive an ACK for the final transmitted data, it concludes that the communication session has ended, at which point it stops any further transmission and sets SDA to high level. If this processing is not performed before the slave starts transmitting the next data, SDA will be pulled low, which will prevent the master device from issuing a stop condition.
When the slave (or master) pulls SCL to low level, communication is stopped (set to wait mode).
Normally, a wait is set either after the eighth clock cycle (when data transfer is completed but before an ACK is returned) or after the ninth clock cycle (when an ACK has been returned but before the next transfer).
A wait is set at the eighth clock cycle when determining whether or not to return an ACK in response to data on the receiving side.
The transmitting side sets a wait after the ACK (at the ninth clock cycle).
This confirms the ACK response and determines the next operation.
In cases such as with EEPROM devices, where the device contains internal address information in addition to the device's own address, the I2C bus's address can only be used to select the device.
The address information that specifies which of the device's memory addresses to use, therefore, must be transmitted as data.
When writing, the write data can be transmitted after the memory address, as shown in the example below.
When reading the data, however, transfer direction must be switched.
A read example is shown below.
Bus access begins when the first start condition is issued, and the device's address is specified (in this time, a transmission from the master is specified).
Afterward, the device's internal address is transmitted as data.
A read operation cannot yet occur, so a second start condition is issued.
ST2 shown in the figure below is the restart condition.
Later, a device is again specified by an address, but this time it specifies transmission by a slave device.
The subsequent data will be transmitted from a slave device to a master device, so a read operation is enabled.
When the data transfer is completed, the bus is released. A stop condition is used to do this.
The master device sets SDA to low level while SCL is already at low level, then it sets SCL to high level.
After this, the stop condition is set when SDA goes to high level.
When writing to an EEPROM, the actual write operation in the device occurs once the stop condition is detected.