The configuration of the CNTR polarity switching bit is shown in the following figure.
This bit determines the output start level when the toggle flip-flop is initialized, for example at the start of pulse output. Also, if this bit is rewritten during pulse output, output level will reverse.
Once toggle flip-flop is initialized, Q = 1 (output polarity "H") and Q = 0 (output polarity "L") are set.
Toggle flip-flop initialization is caused by selecting modes other than pulse output mode.
If the timer count stops, the output level at that time will be retained.
(Ex.1) When CNTR polarity switching bit = 0 at toggle flip-flop initialization
1. Toggle flip-flop Q = 1 initiates pulse output from "H"
2. Toggle flip-flop reverses to Q = 0 due to timer underflow, and pulse output switches to "L" output.
(Ex.2) When CNTR polarity switching bit = 1 at toggle flip-flop initialization
1. Toggle flip-flop Q = 0 initiates pulse output from "L"
2. Pulse output switches to "H" output due to timer underflow.
3. Toggle flip-flop will not initialize even if data is written to the timer latch, and pulse output will remain as "H" output until the next underflow.
* "Timer latch" signifies the timer latch of the applicable timer (timer Z latch, timer Z1 latch or timer Z2 latch).
"CNTR polarity switching bit" signifies the output pin polarity switching bit of the applicable timer (CNTR2 active edge switch bit or CNTR3 active edge switch bit).