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SSU-IIC2-SCI3 output clocks_E8a/E8/E7

Last Updated:10/18/2017

Question:

When a break occurs while debugging an H8/300H Tiny Series MCU with the E8a/E8/E7 emulator, the SSU, IIC2 and SCI3 output clocks. How can this be avoided?

Answer:

This problem occurs when the Synchronous Serial Communication Unit (SSU) SSRDR register, IIC Bus Interface Controller 2 (IIC2) ICDRR register, or Serial Communication Interface 3 (SCI3) RDR register is displayed in the I/O register window or when the register address corresponding to any of these registers is displayed in the memory window.

When the I/O register window or memory window is updated during debug, the debugger reads the register/address displayed in the window and therefore outputs the clock.

The only way to avoid this problem is to not access these registers.
For the I/O window: either do not view any of the registers of the corresponding module in the window or delete the corresponding register description from the [target MCU].io file in the folders listed below, as explained in Supplement E: I/O File Format of the E7 User Manual or in Reference 6: I/O File Format of the High-performance Embedded Workshop User Manual.

E7:
High-performance Embedded Workshop User Manual Install Folder
\Tools\Renesas\DebugComp\Platform\E7\IOFiles

E8:
High-performance Embedded Workshop User Manual Install Folder
\Tools\Renesas\DebugComp\Platform\E8\IOFiles

E8a:
High-performance Embedded Workshop User Manual Install Folder
\Tools\Renesas\DebugComp\Platform\E8a\IOFiles

Memory window: disable the automatic update of the memory window by placing the cursor in the memory window, and selecting [Lock Refresh] with the right-click.

Suitable Products

E7
E8
E8a