Since the RESET pin is used to set the microcontroller mode for the RL78 family microcontroller, the reset signal from the target system is temporarily masked by the E1 or E20 emulator, after which the E1 or E20 emulator transmits the RESET signal to the microcontroller (that is, the RESET pin needs to be controlled from the E1 or E20 emulator).
On the one hand, the states of the individual tri-state buffers in the E1 or E20 emulator are controlled by the output from its FPGA (i.e. by the RD74LVC125B buffer connected to pin 10). However, the RESET pin must be kept at the low level until the standby period of the FPGA ends (to be specific, until the E1 or E20 emulator is physically connected to the target). During this period, the RESET pin is controlled via the DTC124EE connected to pin 13 instead of through processing by the FPGA.
Once the standby period of the FPGA has finished, reset control is applied via pin 10 rather than pin 13.
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