The SCI transmitter/receiver uses double-buffering.
When the TXI interrupt occurs after the 10-byte data transfer has been completed by the DTC, 10th byte of the data has not been transmitted yet from the the SCI. Follow the procedure as follows to clear the TE;
Clear the TEND flag during the TXI interrupt generated after the 10-byte data transfer has been completed by the DTC, and allow the TEI interrupt. Clear the TE during the TEI interrupt generated after the data transmission of 10th byte has been completed.
Also, clear the TDRE flag during the TXI interrupt generatedafter the 10th byte transfer has been comopleted by the DTC (activation source flag cannot be cleared by the last transfer of theDTC).
The last data in the transmit data register (SCTDR) written by the DTC cannot be transferred to the transmit shift register (TSR) if the TDRE is not cleared.
|SH7131, SH7132, SH7136, SH7137|
|SH7083, SH7084, SH7085, SH7086|