(1) Firstly, please check if the CAS latency value of SDRAM set in the wait control register 2 (WCR2) bit 6 and 5(wait control of area 3 (A3W1 and A3W0)) and the CAS latency value of SDRAM set in the synchronous DRAM mode register (SDMR) are right.
(2) Set the burst length of SDRAM to one(1).
(3) As for drawing operation, the cache off area has to be used. The SH7727 LCD controller only accesses to the SDRAM of area 3 and it does not access to the cache.
(4) The LCDC data width of SH7727 is 16-bit. As for the connection with the liquid crystal module that has 18-bit digital interface (RGB=6:6:6), R is five(5), G is six(6), and B is five(5). R and B need the process such as setting each least significant bit to pull-down or pull-up.